A primary factor in the utility of a computer system is its speed in executing application programs. A high-performance computer system is expected to be responsive to user inputs and to accurately provide processed results within real-time constraints. A primary factor in the speed and responsiveness of a computer system is the efficiency of its processor subsystem, memory subsystem, I/O (input output) subsystem, and the like. Large investments have been made in the development of very high-speed processors and high-speed memory subsystems. Consequently, the computer industry has seen remarkable annual improvements in computer system performance. A comparatively new area of focus for improving computer system performance is the input output mechanisms involved in accessing and storing data.
Data is typically stored on attached hard disk drives. Disk drives having a size of 200 GB or more are increasingly common in desktop and laptop computer systems. Fast and efficient access to data stored on such drives is important to responsiveness and functionality of typical user applications.
ATA (AT Attachment) is a widely supported specification that defines methods of accessing data on disks. The ATA specification evolved from the earlier IDE (integrated drive electronics) specification. ATA defines a type of hardware interface that is widely used to connect data storage peripheral devices such as hard disk drives, CD-ROMs, tape drives, and the like, to a computer system. The ATA standard has further evolved to accommodate additional device types and data transfer features. For example, ATAPI (ATA Packet Interface) defines a version of the ATA standard for CD-ROMs and tape drives, ATA-2 (Fast ATA) defines the faster transfer rates used in Enhanced IDE (EIDE), and ATA-3 adds interface improvements, including the ability to report potential problems.
ATA devices have shown dramatic increases in data transfer speed and storage capacity over time. However, computer systems using such faster devices have not fully shown the expected performance improvements. A number of interface problems with computer system I/O components are partially responsible for the performance limitations, such as, for example, the data transfer characteristics of the PCI bus (e.g., due to the need to retain host adapter PCI compatibility), the interrupt based data transfer mechanisms, and the like.
The ADMA (Automatic DMA) specification comprises a new specification designed to improve the performance of ATA type devices. ADMA is designed to add features that improve the data transfer speed and efficiency of ATA devices. For example, ADMA adds support for multi-threading applications, command chaining techniques, command queuing, and the like, which are intended to have the overall effect of decoupling the host command sequence from the channel execution. ADMA attempted to address a number of inefficiencies with the earlier ATA specifications by implementing hardware level support for more modern data transfer mechanisms. The objective of the ADMA standard is to dramatically increase the performance of computer systems that operate with ATA type devices.
Problems remain, however, with respect to the manner in which the prior art ADMA controller architecture implements several of its supposed efficiency enhancing methods. One such problem is excessive disk startup latency. The excessive startup latency is due to the fact that the transfer of transaction information from the processor to system memory and then to the disk controller involves a number of arbitration and transfer operations on the buses linking the processor, system memory, and disk controller. These bus transactions can each incur two to four microseconds of latency. Another another startup latency problem is due to the fact that the disk controller does not start the disk drive mechanism to begin transaction until it has received the transaction information (e.g. via DMA transfer) from system memory.
Another problem is the manner in which additional disk transaction commands are queued for completion. The prior art ADMA specification implements a command chaining techniques in order to enable multiple disk I/O commands to be outstanding simultaneously. The prior art ADMA specification relies upon a system of memory locks to maintain the coherency of the pointers of a command chain (e.g., a CPB chain). The memory locks are implemented in order to ensure only one software process, or thread, can manipulate a CPB chain at a time. This can be very inefficient in a modern computer system having a modern, multithreaded, multiprocess software execution environment.
Another problem is the manner in which the computer system is notified of the completion of the pending disk I/O commands. The prior art ADMA specification relies on an interrupt servicing mechanism to notify the computer system of completed disk I/O commands. Unfortunately, the prior art interrupt servicing mechanism causes an excessive number of disk I/O interrupts. The excessive number of disk I/O interrupts imposes a substantial overhead burden on the computer system. For example, each interrupt servicing typically requires the computer system to switch context from its current process. Context switching consumes a significant number of CPU cycles.
Thus, the overhead problems of the prior art ADMA controller architecture can significantly detract from overall computer system performance. As processor and system memory performance continue to show annual improvement, it becomes increasingly important that disk I/O systems show similar improvements. As latency penalties are reduced in other components of a computer system (e.g., data transfer buses, graphics operations, etc.) it becomes increasingly important that the disk I/O system shows similar degrees of improvement in order to avoid imposing performance bottlenecks on the overall computer system.